1. Field of the Invention
The present invention generally relates to physical circuit design and more particularly to reducing design to hardware time for Very Large Scale Integrated (VLSI) circuit designs, especially Very Deep Submicron (VDSM) VLSI.
2. Background Description
State of the art integrated circuit (IC) logic chips have logic that may be interactively placed and wired, principally, based upon logic timing. Generally, for a typical synchronous logic chip, logic paths are bracketed by flip flops or registers that are clocked by on-chip clocks, i.e., a clock sets a flip flop at the beginning of a path and after a given (clock) period, the results are locked in a second flip flop at the other end of the path. So, the time between clock edges determines how much time is available for a signal to propagate along the particular path. Since an initial placement is a coarse placement, it likely to include paths that would fail in hardware.
In what is known as Static Timing Analysis (STA), path delays are calculated for the entire design, block-by-block, gate-by-gate, net wire-by-wire. After STA, the designer can identify any failing paths, i.e., where the path delay is longer than the available time. STA also identifies any extra time between the calculated propagation delay time and the clock period, which is known as slack. Normally by design, there is a required minimum amount of slack specified. Thus, after STA one may determine any path with less than that specified required amount of slack, i.e., what is known as a critical path. Critical paths are most sensitive to process, voltage or temperature variations or anything else that might change path timing, and so, most likely to encounter timing related problems.
Thus, typically, chip design is iterative, with the designer using STA results from one iteration to determine each critical or failing path and its associated nets are, e.g., using what is known as a slack graph for the logic that indicates slack in individual paths. STA performs a gate-by-gate response analysis, iteratively for each gate determining an effective capacitance for the gate and a gate response to that effective capacitance. Typically, in each iteration an effective capacitance is calculated based on an output transition slew from the previous iteration and, a new output transition slew is determined, e.g., retrieved from a look up table. After determining a response for each gate, path delays may be determined as the sum of gate responses for each particular path. Only after determining path delays, may the designer identify design sensitivities or failures for the current chip design pass.
After identifying design sensitivities or failures, the chip designer may adjust the design to eliminate both failing and, where possible, critical paths, e.g., by relocating some logic in the critical paths to non-critical paths. Normally, after identifying critical paths, only those critical path nets are considered for optimization to eliminate criticalities, e.g., re-locating cells, re-powering cells and in severe cases, redesigning logic for the critical path. This is a long arduous task. Further, redesigning one book or net in the critical path is not considered with respect to its affect on other nets in other critical paths that might also include the redesigned critical net. Consequently, redesigning one net in one critical path might help or hinder fixing other critical paths. So, after each re-design iteration the designer must again use STA to locate and eliminate critical paths.
Accordingly, it is becoming increasingly important for design success to improve STA accuracy and efficiency, especially as technology dimensions reach very deep into the sub-micron and nanometer range. These smaller features increase the per unit gate density for logic chips, even as chip size is increasing. Thus, chip density is increasing geometrically. Consequently, even if the time to calculate each individual gate response is reduced, STA time is increasing dramatically.
Thus, there is a need for an reducing chip design time and more particularly, for reducing the design time required for Static Timing Analysis (STA).